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CY25000
Programmable Spread Spectrum Clock Generator for EMI Reduction
Features
* Wide operating output (SSCLK) frequency range -- 3-200 MHz * Programmable spread spectrum with nominal 30-kHz modulation frequency -- Center spread: 0.25% to 2.5% -- Down spread: -0.5% to -5.0% * Input frequency range -- External crystal: 8-30 MHz fundamental crystals -- External reference: 8-166 MHz Clock * Integrated phase-locked loop (PLL) * Programmable crystal load capacitor tuning array * Low cycle-to-cycle Jitter * 3.3V operation * Spread spectrum On/Off function * Power-down or Output Enable function
Benefits
* Services most PC peripherals, networking, and consumer applications. * Provides wide range of spread percentages for maximum EMI reduction, to meet regulatory agency Electro Magnetic Compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market. * Eliminates the need for expensive and difficult to use higher order crystals. * Internal PLL to generate up to 200-MHz output. Able to generate custom frequencies from an external crystal or a driven source. * Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal. Eliminates the need for external CLoad capacitors. * Suitable for most PC, consumer, and networking applications * Application compatibility in standard and low-power systems. * Provides ability to enable or disable spread spectrum with an external pin. * Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
XIN/CLKIN 1 XOUT 8 CXOUT
OSC. CXIN
PLL with Modulation Control Output Dividers and MUX
6 REFCLK 5 SSCLK
Pin Configuration
CY25000 8-pin SOIC
XIN/CLKIN VDD PD#/OE VSS 1 2 3 4 8 7 6 5 XOUT SSON REFCLK SSCLK
Programmable Configuration
PD#/OE 3 SSON 7
2
4
VDD VSS
Cypress Semiconductor Corporation Document #: 38-07424 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised September 26, 2003
CY25000
Pin Descriptions
Pin 1 2 3 4 5 6 7 8 Name XIN/CLKIN VDD PD#/OE VSS SSCLK REFCLK SSON XOUT 3.3V voltage supply. Power-down pin. Active LOW. If PD# = 0, SSCLK and REFCLK are three-stated. Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled. User has the option of choosing either PD# or OE function. GND. Spread spectrum clock output. Buffered reference output. Spread spectrum control. 1 = Spread on. 0 = Spread off. Crystal output. Leave this pin floating if external clock is used. The spread % is factory programmed to either center spread or down spread with various spread percentages. The range for center spread is from 0.25% to 2.50%. The range for down spread is from -0.5% to -5.0%. Contact the factory for smaller or larger spread % amounts if required. The input to the CY25000 can be either a crystal or a clock signal. The input frequency range for crystals is 8-30 MHz, and for clock signals is 8-166 MHz. The CY25000 has two clock outputs, REFCLK and SSCLK. The non-spread spectrum REFCLK output has the same frequency as the input of the CY25000. The frequency modulated SSCLK output can be programmed from 3-200 MHz. The CY25000 products are available in an 8-pin SOIC (150-mil) package with a commercial operating temperature range of 0 to 70C. Description Crystal input or reference clock input.
General Description
The CY25000 is a Spread Spectrum Clock Generator (SSCG) IC used for the purpose of reducing Electro Magnetic Interference (EMI) found in today's high-speed digital electronic systems. The device uses a Cypress-proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements (EMC) and improve time to market without degrading system performance. The CY25000 uses a factory-programmable configuration memory array to synthesize output frequency, spread %, crystal load capacitor, reference clock on/off and PD#/OE options.
Document #: 38-07424 Rev. *B
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CY25000
Absolute Maximum Rating
Supply Voltage (VDD) ........................................-0.5 to +7.0V DC Input Voltage...................................... -0.5V to VDD + 0.5 Storage Temperature (Non-Condensing) .... -55C to +125C Junction Temperature ................................ -40C to +125C Data Retention @ Tj=125C................................. > 10 Years Package Power Dissipation...................................... 350 mW Static Discharge Voltage.......................................... > 2000V (per MIL-STD-883, Method 3015)
Operating Conditions
Parameter VDD TA CLOAD Fref Supply Voltage Ambient Temperature Max. Load Capacitance @ pin 5 and pin 6 External Reference Crystal (Fundamental tuned crystals only) External Reference Clock FSSCLK FREFCLK tPU SSCLK output frequency, CLOAD = 15 pF REFCLK output frequency, CLOAD = 15 pF Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 8 8 3 8 0.05 Description Min. 3.13 0 Typ. 3.30 Max. 3.45 70 15 30 166 200 166 500 Unit V C pF MHz MHz MHz MHz ms
DC Electrical Characteristics
Parameter IOH IOL VIH VIL IIH IIL IOZ CXIN/CXOUT[1, 2] CIN[1] IVDD IDDS Description Output High Current Output Low Current Input High Voltage Input Low Voltage Condition VOH = VDD - 0.5, VDD = 3.3V (source) VOL = 0.5, VDD= 3.3V (sink) CMOS levels, 70% of VDD CMOS levels, 30% of VDD Min. 10 10 0.7VDD 0.3VDD 10 10 -10 12 60 5 25 7 35 10 Typ. 14 14 Max. Unit mA mA V V A A A pF pF pF mA
Input High Current, PD#/OE Vin = VDD and SSON pins Input Low Current, PD#/OE Vin = VSS and SSON pins Output Leakage Current Three-state output, PD#/OE = 0 Programmable Capacitance Capacitance at minimum setting at pin 1 and pin 8 Capacitance at maximum setting Input Capacitance at pin 3 and pin 7 Supply Current Input pins excluding XIN and XOUT VDD = 3.45V, Fin = 30 MHz, REFCLK = 30 MHz, SSCLK = 66 MHz, CLOAD = 15 pF, PD#/OE = SSON = VDD VDD = 3.45V, Device powered down with PD#/OE = 0V
Stand by current
15
30
A
AC Electrical Characteristics[1]
Parameter DC Description Output Duty Cycle Output Duty Cycle SR1 SR2 Rising Edge Slew Rate Falling Edge Slew Rate Condition SSCLK, Measured at VDD/2 REFCLK, Measured at VDD/2 Duty Cycle of CLKIN = 50%. SSCLK from 3 to 100 MHz; REFCLK from 10 to 100 MHz. 20%-80% of VDD SSCLK from 3 to 100 MHz; REFCLK from 10 to 100 MHz. 80%-20% of VDD Min. 45 40 0.7 0.7 Typ. 50 50 1.1 1.1 Max. 55 60 1.5 1.5 Unit % % V/ns V/ns
Notes: 1. Guaranteed by characterization, not 100% tested. 2. Contact factory for desired crystal load programming.
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CY25000
AC Electrical Characteristics[1]
Parameter SR3 SR4 tj1 Description Rising Edge Slew Rate Falling Edge Slew Rate Peak Cycle-to-Cycle Jitter. SSCLK pin Peak Cycle-to-Cycle Jitter, REFCLK Power-down Time (pin3 = PD#) Output Disable Time (pin3 = OE) Output Enable Time (pin3 = OE) Power-up Time, Crystal is used Power-up Time, Reference clock is used Condition SSCLK from 100 to 200 MHz; REFCLK from 100 to 166 MHz 20%-80% of VDD SSCLK from 100 to 200 MHz; REFCLK from 100 to 166 MHz 80%-20% of VDD SSCLK = 200 MHz. Spread on SSCLK = 66 MHz. Spread on SSCLK = 14.3 MHz. Spread on tj2 tSTP TOE1 TOE2 tPU1 tPU2 Table 1. Pin Function Pin Name Pin# Units PROGRAM VALUE Input Frequency XIN and XOUT 1 and 8 MHz ENTER DATA CXIN and CXOUT XIN and XOUT 1 and 8 pF Output Frequency SSCLK 5 MHz Spread Percent SSCLK 5 % ENTER DATA Reference Output REFOUT 6 On or Off ENTER DATA Power-down or Output Enable PD#/OE 3 Select PD# or OE ENTER DATA Frequency Modulation SSCLK 5 kHz 30 REFCLK output only Time from falling edge on PD# to stopped outputs (Asynchronous) Time from falling edge on OE to stopped outputs (Asynchronous) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) Time from rising edge on PD# to outputs at valid frequency (Asynchronous) Time from rising edge on PD# to outputs at valid frequency (Asynchronous) Min. 1.2 1.2 Typ. 1.6 1.6 100 150 200 100 150 150 150 3 2 Max. 2.0 2.0 200 300 400 200 300 300 300 5 3 Unit V/ns V/ns ps ps ps ps ns ns ns ms ms
ENTER DATA ENTER DATA
Programming Description
The customers planning to use the CY25000 need to provide the programming information described as "ENTER DATA" in Table 1 and should contact local Cypress Sales. Additional information on the CY25000 can be obtained from the Cypress web site at www.cypress.com.
CXIN = CXOUT = 2CL - CP Where CL is the crystal load capacitor as specified by the crystal manufacturer and CP is the parasitic PCB capacitance. For example, if a fundamental 16-MHz crystal with CL of 16 pF is used and CP is 2 pF, CXIN and CXOUT can be calculated as: CXIN = CXOUT = (2 x 16) - 2 = 30 pF. If using a driven reference, set CXIN and CXOUT to the minimum value 12 pF. Output Frequency, SSCLK Output (SSCLK, pin 5) The modulated frequency at the SSCLK output is produced by synthesizing the input reference clock. The modulation can be stopped by SSON digital control input (SSON = LOW, no modulation). If modulation is stopped, the clock frequency is the nominal value of the synthesized frequency without modulation (spread % = 0). The range of synthesized clock is from 3-200 MHz. Spread Percentage (SSCLK, pin 5) The SSCLK frequency can be programmed at any percentage value from 0.25% to 2.5% for Center Spread and from -0.5% to -5.0% Down Spread.
Product Functions
Input Frequency (XIN, pin 1 and XOUT, pin 8) The input to the CY25000 can be a crystal or a clock. The input frequency range for crystals is 8 to 30 MHz, and for clock signal is 8 to 166 MHz. CXIN and CXOUT (pin 1 and pin 8) The load capacitors at pin 1 (CXIN) and pin 8 (CXOUT) can be programmed from 12 pF to 60 pF with 0.5-pF increments. The programmed value of these on-chip crystal load capacitors are the same (XIN = XOUT = 12 to 60 pF). The required values of CXIN and CXOUT can be calculated using the following formula:
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CY25000
Reference Output (REFOUT, pin 6) The reference clock output has the same frequency and the same phase as the input clock. This output can be programmed to be enabled (clock on) or disabled (High-Z, clock off). If this output is not needed, it is recommended that users request the disabled (High-Z, Clock Off) option. Frequency Modulation The frequency modulation is programmed at 30 kHz for all SSCLK frequencies from 3 to 200 MHz. Contact the factory if a higher modulation frequency is required. Power-down or Output Enable (PD# or OE, pin 3): Users can select either PD# or OE function which are also factory programmable.
Application Circuit[3, 4, 5]
Crystal
Power
XIN 1 8
XOUT
CY25000
VDD 0.1F VDD PD#/OE VSS
2 3 4
7 6 5
SSON REFCLK SSCLK
VDD
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B)
OUTPUT t1A t1B
Output Rise/Fall Time (SSCLK and REFCLK)
VDD 0V
Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
OUTPUT
Power-down Timing and Power-up Timing
POWERDOWN VDD 0V VIL VIH tPU
(Asynchronous)
CLKOUT tSTP
High Impedance
Notes: 3. Since the load capacitors (CXIN and CXOUT) are provided by the CY25000, no external capacitors are needed on the XIN and XOUT pins to match the crystal load capacitor (CL). Only a single 0.1-F bypass capacitor is required on the VDD pin. 4. If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected). 5. If SSON (pin 7) is LOW (VSS), the frequency modulation will be stopped on SSCLK pin (pin 5).
Document #: 38-07424 Rev. *B
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CY25000
Switching Waveforms (continued)
Output Enable/Disable Timing
OUTPUT ENABLE VDD 0V VIL VIH TOE2
(Asynchronous
CLKOUT
High Impedance TOE1
)
Informational Graphs
172.5 171.5 170.5 169.5 168.5 167.5 166.5 165.5 164.5 163.5 162.5 161.5 160.5 159.5
0 20 40 60 80 100 120 Time (us) 140 160 180 200
Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4%
Fnominal
169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 162.5
0 20
Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1%
Fnominal
40
60
80
100 120 Time (us)
140
160
180
200
68.5 68 67.5 67 66.5 66 65.5 65 64.5 64 63.5
0 20
Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4%
67.5 67 66.5
Fnominal
Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1%
66 65.5 65 64.5
Fnominal
40
60
80
100 120 Time (us)
140
160
180
200
0
20
40
60
80
100 120 Time (us)
140
160
180
200
Document #: 38-07424 Rev. *B
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CY25000
Informational Graphs (continued)
Duty Cycle vs. REFCLK (VDD=3.0V, Temperature=25C, CLOAD = 15pF)
60 58 56 Duty Cycle (%) 54 52 50 48 46 44 42 40 0 50 100 REFCLK (MHz) 150 200
IDD vs. SSCLK Temperature=25C, VDD=3.3V, CLOAD=15pF
70 60 50 40 30 20 10 0 0 50 100 150 200 250
REFCLK=SSCLK REFCLK=30MHz
SSC LK (M H z)
Measured Spread% vs. VDD over Tem perature (Target Spread = 0.5%, Fout=100MHz, CLOAD=15pF) 0.60% Spread% 0.55% 0.50% 0.45% 0.40% 2.7 3 3.3 VDD (V) 3.6 3.9
Spread%
Measured Spread% vs. VDD over Tem perature (Target Spread = 5.0%, Fout=100MHz, CLOAD=15pF) 6.00% 5.50% 5.00% 4.50% 4.00% 2.7 3 3.3 VDD (V) 3.6 3.9 -40C 25C 85C
-40C 25C 85C
SSCLK Attenduation vs. VDD over Tem perature (Measured at 7th Harmonic w ith Fnom=100MHz and Spread=0.5%, CLOAD=15pF) 0 -2 -4 -6 -8 -10 2.7 3 3.3 VDD (V) 3.6 3.9 -40C 25C 85C
SSCLK Attenduation vs. VDD over Tem perature (Measured at 7th Harmonic w ith Fnom=100MHz and Spread=5.0%, CLOAD=15pF) -10 -12 -14 -16 -18 -20 2.7 3 3.3 VDD (V) 3.6 3.9
Attenuation (dB)
Attenuation (dB)
-40C 25C 85C
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CY25000
Informational Graphs (continued)
SSCLK Attenuation vs. Spread% (Temp=25C, VDD=3.3V, SSCLK=100MHz, Measured on Cypress Characterization board w ith CLOAD=15pF)
0 -2 -4 -6 -8 -10 -12 -14 -16 0.0% 0.5% 1.0% 1.5% 2.0% 2.5% 3.0% 3.5% 4.0% 4.5% 5.0% -60 -40 - 20
Max Cycle-Cycle Jitter on SSCLK vs. Tem perature (SSCLK=100MHz, VDD=3.3V, CLOAD=15pF)
200 175 150 125 100 75 50 25 0 0 20 40 60 80 100
S pre a d %
T e m p ( de g C )
Custom Configuration Request Procedure
The CY25000 is a memory programmable device that is configured in the factory. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. A sample request form (refer to "CY25000 Sample
Request Form" at www.cypress.com) must be completed. Once the request has been processed, you will receive a new part number, samples and data sheet with the programmed values. This part number will be used for additional sample requests and production orders.
Ordering Information
Part Number[6] CY25XXXSC-W CY25XXXSC-WT Package Type 8-pin Small Outline Integrated Circuit (SOIC) 8-pin Small Outline Integrated Circuit (SOIC)-Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C
Document #: 38-07424 Rev. *B
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CY25000
Package Drawing and Dimensions
8 Lead (150 Mil) SOIC -8-lead (150-Mil) SOIC S8 S08
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
0.0138[0.350] 0.0192[0.487]
51-85066-*C
Note: 6. "XXX" denotes the assigned product number. "W" denotes the different programmed spread % values. The user can request different spread % values.
All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY25000
Document History Page
Document Title: CY25000 Programmable Spread Spectrum Clock Generator for EMI Reduction Document Number: 38-07424 REV. ** *A *B ECN NO. Issue Date 115076 121901 129855 06/20/02 12/14/02 10/01/03 Orig. of Change CKN RBI RGL New Data Sheet Power-up requirements added to Operating Conditions Information Removed "PRELIMINARY" Changed IOH and IOL min. from 12 mA to 10 mA and typical from 24 mA to 14 mA Description of Change
Document #: 38-07424 Rev. *B
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